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MAX15024/MAX15025
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Pin Description
PIN
MAX15024
MAX15025A
MAX15025B
MAX15025C
MAX15025D
NAME
FUNCTION
LDO Regulator Output Set. Feedback for V REG adjustment (V FB > 200mV).
1
1
1
FB/SET
Connect FB/SET to GND for a fixed 10V output REG. Connect FB/SET to a
resistor ladder to set V REG .
Power-Supply Input. Bypass to GND with a low-ESR ceramic capacitor of
2
2
2
V CC
1μF. Input of the internal housekeeping regulator and of the main REG
regulator.
3
4
—
5
—
—
6
7
—
8
—
3
—
4
—
5
—
6
—
7
—
8
3
—
4
—
—
5
6
—
7
—
8
GND
IN+
IN1
IN-
IN2
IN2
PGND
N_OUT
OUT2
P_OUT
OUT1
Signal Ground
Driver Noninverting Logic Input. Connect to V CC when not used.
Driver 1 Noninverting Logic Input
Driver Inverting Logic Input. Connect to GND when not used.
Driver 2 Noninverting Logic Input
Driver 2 Inverting Logic Input
Power Ground. Sink current return. Source of the internal pulldown
n-channel transistor.
Sink Output. Open-drain n-channel output. N_OUT sinks current for power
MOSFET turn-off.
Driver 2 Output
Source Output. Pullup p-channel output (open drain). Sources current for
power MOSFET turn-on.
Driver 1 Output
Output Driver Supply Voltage. Decouple DRV with a low ESR > 0.1μF
ceramic capacitor to PGND placed in close proximity to the device. DRV
9
9
9
DRV
can be powered independently from REG. Connect DRV, REG, and V CC
together when there is no need for special DRV supply sequencing and
the power-MOSFET gate voltage does not need to be regulated or limited.
Voltage Regulator Output. Connect to DRV for driving the power MOSFET
10
10
10
REG
with regulated V GS amplitude. Bypass with a low-ESR 1μF (minimum)
ceramic capacitor to GND placed in close proximity to the device to
ensure regulator stability.
Exposed Pad. Internally connected to GND. Connect to GND plane or
—
—
—
EP
thermal pad and use multiple vias to a solid copper area on the bottom of
the PCB.
Maxim Integrated
9
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